PZT压电薄膜成积
PZT性能和工艺特点
- 生长温度<500C,CMOS兼容
- PZT薄膜生长厚度:5~5um,均匀性±2%
- PZT压电性能:e31~14.9C/m2
- PZT应力<100MPa
- 薄膜击穿电压:Vbreakdown~40V/um
不同衬底的PZT生长实现
- 单抛&双抛硅片
- SOI硅片
- Cavity SOI硅片
- 硅光晶圆基底
- 玻璃/不锈钢/ITO
PZT晶圆
通过用贵金属电极夹持数µm的铁电体,形成压电元件。
工艺结构:TiOx/Pt/Buffer/PZT/Pt。
ULVAC 提供的溅射设备可稳定沉积世界最高水平的 PZT 溅射膜。(CMOS上成膜对应:PZT成膜温度 < 500°C)搭载多腔室,可成膜PZT full stack(上下电极+PZT)。

溅射性能
| No. | Spec. |
| 1 | Ti film thickness Uniformity Within ±5% |
| 2 | LNO film thickness Uniformity Within ±10% |
| 3 | PZT film thickness Uniformity Within ±5% |
| 4 | PZT deposition rate > 4 μm/h (measured at film thickness 1 μm) |
| 5 | PZT Deposition Temperature < 500℃ |
| 6 | Film stack PZT/buffer: < +70 MPa |
| 7 | Surface roughness < 40 nm RMS (Area : 5 μm × 5 μm) |
| 8 | |e₃₁, f| > 13.0 C/m² (1 μm) Measure 1 point (center) for each wafer |
| 9 | |e₃₁, f| uniformity ±10% Measure 5 points for each wafer |
| (±5%+5%Measurement error=10%) ※Edge ex. 10mm | |
| 10 | Breakdown voltage > |-40 V| Measure 3 points (Center, Middle, Edge) for each wafer ※Edge ex. 10 mm |
| 11 | Dielectric constant: Data submission |
| 12 | Dielectric loss < 0.06(10 V, 1 kHz) |
| 13 | Piezoelectric fatigue after 1E+10cycles e31 Degradation <10% |
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